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| KBE00F005A-D411 mcp memory june 2005 1 revision 1.0 mcp specification 512mb nand*2 + 256mb mobile sdram*2 * samsung electronics reserves the right to chang e products or specification without notice. information in this document is provid ed in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for us e in life support, critical care, m edical, safety equipment, or similar applications where product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any government al procurement to which special terms or provisions may apply.
june 2005 2 KBE00F005A-D411 mcp memory revision 1.0 document title multi-chip package memory 512m bit(64mx8) nand flash*2 / 256m bit (2mx32x4ban ks) mobile sdram*2 revision history the attached datasheets are prepared and approved by samsung el ectronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you h ave any questions, please contact the samsung branch office near you. revision no. 0.0 1.0 remark preliminary final history initial issue. - 1gb nand flash ddp b-die _ ver 0.1 - 512mb mobile sdram ddp f-die _ ver 1.0 june 2005 3 KBE00F005A-D411 mcp memory revision 1.0 general description features june 2005 4 KBE00F005A-D411 mcp memory revision 1.0 pin configuration 137 fbga: top view (ball down) nand m-sdr 12345678 nc cle vcc ce we n vdd vss a4 wp ale vss r/b dq31 dq30 vddq a5 dq25 dq27 dq29 dq28 vssq a8 dq18 nc dq22 dqm3 dq26 vddq a11 dq17 dq19 dq24 dq23 ras dq15 dq16 dq9 vddq cas dq20 dq21 nc nc vss cs dq14 dq11 dq10 nc dqm0 vssq ba1 dq7 dq8 dq6 dq4 vddq a2 dq0 dq1 dq2 dq3 dq5 vddq vss nc nc vssq io2 vcc io6 vddq a b c d e f g h j k l m vssq dqm2 dnu nc dnu dnu nc vssq vss nc n p nc dqm1 dq13 dq12 9 10 vss vdd a6 a12 nc vdd vss we d a1 vdd vssq vddq vssq vssq vdd vddq vssq vssq vddq vddq vss io4 vdd dnu dnu dnu dnu r io3 io5 io7 nc nc nc nc nc re a7 a9 cke clk ba0 a0 a10 a3 io0 io1 nc nc nc nc cs 1 june 2005 5 KBE00F005A-D411 mcp memory revision 1.0 note : 1. samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life i s potentially at stake. please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for a ny specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. ordering information samsung mcp memory(4chips) device type nand + nand + sdram+sdram nor flash density, voltage, organization, bank size, boot block 00 = none access time 411 : nand flash 50ns nand flash 50ns mobile sdram 9ns mobile sdram 9ns sdram interface, density, voltage, organization, option 5 = m-sdr, 256m+256m, 1.8v/1.8v, x32 u t ram density, voltage, organization 0 = none package d = fbga(lead-free) nand flash density, voltage, organization f = 512m+512m, 2.7v/2.7v, x8 sram density, voltage, organization 0 = none kb e 00 f 0 0 5 a - d 411 version a = 2nd generation pin description pin name pin function(mobile sdram) clk system clock cke clock enable cs ,cs 1 chip select ras row address strobe cas column address strobe we d write enable a0 ~ a12 address input ba0 ~ ba1 bank address input dqm0 ~ dqm3 input/output data mask dq0 ~ dq31 data input/output vdd power supply vddq data out power vss ground vssq dq ground pin name pin function(nand flash) ce chip enable re read enable wp write protection we n write enable ale address latch enable cle command latch enable r/b ready/busy output io0 ~ io7 data input/output vcc power supply vss ground pin name pin function nc no connection dnu do not use KBE00F005A-D411 mcp memory june 2005 6 revision 1.0 functional block diagram wp cle we n re r/b ce io0 to io7 cs cas ras cke we d clk a0~a12 dqm0~dqm3 ba0~ba1 ale 1gb nand flash memory dq0 to dq31 512mb mobile sdram v dd v ddq v cc v ss v ss v ssq cs 1 KBE00F005A-D411 mcp memory june 2005 7 revision 1.0 1gb(128mb x 8) nand flash ddp b-die KBE00F005A-D411 mcp memory june 2005 8 revision 1.0 pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and da ta, and to output data dur ing read operations. the i/ o pins float to high-z when the chip is des elected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for command s sent to the command register. when active high, commands are latched into the command register th rough the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for address to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase operation. regarding ce control during read operation, refer to ?page re ad? section of device operation . re read enable the re input is the serial data-out control, and when acti ve drives the data onto the i/o bus. data is valid trea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent write/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. r/b ready/busy output the r/b output indicates the status of the device operati on. when low, it indicates that a program, erase or random read operation is in process and returns to hi gh state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. vcc q output buffer power vcc q is the power supply for output buffer. vcc q is internally connected to vcc, thus should be biased to vcc. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. dnu do not use leave it disconnected. KBE00F005A-D411 mcp memory june 2005 9 revision 1.0 512b bytes 16 bytes figure 1. functional block diagram figure 2. array organization note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the starting address of the 2nd half of the register. * a 8 is set to "low" or "high" by the 00h or 01h command. * l must be set to "low". i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 a 24 4th cycle a 25 a 26 *l *l *l *l *l *l v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 9 - a 26 a 0 - a 7 command ce re we cle wp i/0 0 i/0 7 v cc v ss a 8 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 256k pages (=8,192 blocks) 512 bytes 8 bit 16 bytes 1 block = 32 pages (16k + 512) byte i/o 0 ~ i/o 7 1 page = 528 bytes 1 block = 528 b x 32 pages = (16k + 512) bytes 1 device = 528b x 32pages x 8,192 blocks = 1,056 mbits column address row address (page address) page register ale 1,024m + 32m bit nand flash array (512 + 16)byte x 262,144 y-gating page register & s/a KBE00F005A-D411 mcp memory june 2005 10 revision 1.0 product introduction this device is a 1,026mbit(1,107,296,436 bi t) memory organized as 262,144 rows(pages) by 528 columns. spare sixteen columns are located from column address of 512 to 527. a 528-byte data register is connected to memory cell arrays accommodating data transfer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected to form a nand structure. each of the 16 cells resides in a different page. a block consists of two nand structured strings. a nand structure consists of 16 cells. total 135168 nand cells reside in a block. the array organizati on is shown in figure 2. the program and read operations are executed on a page basis, while the erase operation is executed on a blo ck basis. the memory array consists of 8,192 separately erasable 16k-byte blocks. it indicates that the bit by bit erase operation is pro- hibited on this device. this device has addresses multiplexed into 8 i/o's. this schem e dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board des ign. command, address and data are all written through i/o's by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respective ly, via the i/o pins. the 128m byte physical space requires 27 addresses, thereby requiring four cycles for byte-level addressi ng: column address, low row address and high row address, in th at order. page read and page program need the same four address cycl es following the required command input. in block erase oper- ation, however, only the three row address cycles are used. device operations are selected by writing specific commands into th e command register. table 1 defines the specific commands of this device. the device provides simultaneous program/erase capability up to four pages/blocks. by dividing the memory array into eight 128m bit separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4x while still maintain ing the conventional 512 byte structure. the extended pass/fail status for multi-plane program/erase allo ws system software to quickly identify the failing page/block o ut of selected multiple pages/blocks. usage of multi-plane o perations will be described further throughout this document. in addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to anot her of the same plane without the need for transporting the data to and from the external buffer memory. since the time-consuming b urst- reading and data-input cycles are removed, system performance fo r solid-state disk application is significantly increased. table 1. command sets note : 1. the 00h command defines starting address of the 1st half of registers. the 01h command defines starting address of the 2nd half of registers. after data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. 2. page program(true) and copy -back program(true) are available on 1 plane operation. page program(dummy) and copy-back program (dummy) are available on the 2nd,3rd,4th plane of multi plane operatio n. 3. the 71h command should be used for read status of multi plane operation. 4. multi plane operation and copy-back program are not supported with 1.8v device. caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st. cycle 2nd. cycle 3rd. cycle acceptable command during busy read 1 00h/01h (1) -- read 2 50h - - read id 90h - - reset ffh - - o page program (true) (2) 80h 10h - page program (dummy) (2) 80h 11h - copy-back program(true) (2) 00h 8ah 10h copy-back program(dummy) (2) 03h 8ah 11h block erase 60h d0h - multi-plane block erase 60h---60h d0h - read status 70h - - o read multi-plane status 71h (3) -- o KBE00F005A-D411 mcp memory june 2005 11 revision 1.0 the device is arranged in eight 128mbit memory planes. each plane contains 1,024 blocks and 528 byte page registers. this allow s it to perform simultaneous page program and block erase by selecting one page or block from each plane. the block address map is configured so that multi-plane program/eras e operations can be executed for every four sequential blocks by dividing the memory array into plane 0~3 or plane 4~7 separately. for example, multi-plane program/erase operations into plane 2,3,4 and 5 are proh ib- ited. plane 0 plane 1 plane 2 plane 3 (1024 block) (1024 block) (1024 block) (1024 block) page 0 page 1 page 31 page 30 memory map block 0 page 0 page 1 page 31 page 30 block 1 page 0 page 1 page 31 page 30 block 2 page 0 page 1 page 31 page 30 block 3 page 0 page 1 page 31 page 30 block 4092 page 0 page 1 page 31 page 30 block 4093 page 0 page 1 page 31 page 30 block 4094 page 0 page 1 page 31 page 30 block 4095 page 0 page 1 page 31 page 30 block 4096 page 0 page 1 page 31 page 30 block 4097 page 0 page 1 page 31 page 30 block 4098 page 0 page 1 page 31 page 30 block 4099 page 0 page 1 page 31 page 30 block 8188 page 0 page 1 page 31 page 30 block 8189 page 0 page 1 page 31 page 30 block 8190 page 0 page 1 page 31 page 30 block 8191 528byte page registers figure 3. memory array map 528byte page registers 528byte page registers 528byte page registers 528byte page registers 528byte page registers 528byte page registers 528byte page registers plane 4 plane 5 plane 6 plane 7 (1024 block) (1024 block) (1024 block) (1024 block) KBE00F005A-D411 mcp memory june 2005 12 revision 1.0 recommended operating conditions (voltage reference to gnd , t a =-25 to 85 c) parameter symbol value unit min typ. max supply voltage v cc 2.5 2.7 2.9 v supply voltage v ccq 2.5 2.7 2.9 v supply voltage v ss 000v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc, +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings ar e exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended peri ods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in/out -0.6 to + 4.6 v v cc -0.6 to + 4.6 v ccq -0.6 to + 4.6 temperature under bias t bias -40 to +125 c storage temperature t stg -65 to +150 c short circuit current ios 5 ma KBE00F005A-D411 mcp memory june 2005 13 revision 1.0 dc and operating characteristics (recommended operating condit ions otherwise noted.) note : v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less parameter symbol test conditions value unit min typ max operating current sequential read i cc 1 trc=50ns, ce =v il i out =0ma -1020 ma program i cc 2--1020 erase i cc 3--1020 stand-by current (ttl) i sb 1ce =v ih , wp =0v/v cc --1 stand-by current (cmos) i sb 2ce =v cc -0.2, wp =0v/v cc -1050 a input leakage current i li v in =0 to vcc(max) - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 input high voltage v ih* i/o pins v ccq -0.4 - v ccq +0.3 v except i/o pins v cc -0.4 - v cc +0.3 input low voltage, all inputs v il* - -0.3 - 0.5 output high voltage level v oh i oh -100 a v ccq -0.4 -- output low voltage level v ol i oh =100 a--0.4 output low current (r/b ) i ol (r/b )v ol =0.1v 3 4 - ma valid block note : 1. the device may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid blocks is pre- sented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits. do not try to access these invalid blocks for program and erase. refer to the attached technical notes for an appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is guar anteed to be a valid block, does not require error correction u p to 1k program/erase cycles. 3. minimum 1004 valid blocks are guaranteed for each contiguous 128mb memory space. parameter symbol min typ. max unit valid block number n vb 8,052 - 8,192 blocks KBE00F005A-D411 mcp memory june 2005 14 revision 1.0 program / erase characteristics parameter symbol min typ max unit program time t prog (1) - 200 500 s dummy busy time for multi plane program t dbsy 110 s number of partial program cycles in the same page main array nop - - 1 cycle spare array - - 2 cycles block erase time t bers -23ms capacitance ( t a =25 c, v cc =2.7v , f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 20 pf input capacitance c in v in =0v - 20 pf ac test condition (ta=-25 to 85 c , vcc=2.5v~2.9v unless otherwise noted) parameter value input pulse levels 0v to vcc q input rise and fall times 5ns input and output timing levels vcc q /2 output load (vcc q :2.7v +/-10%) 1 ttl gate and cl=30pf mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode hll hx read mode command input l h l h x address input(4clock) hll hh write mode command input l h l h h address input(4clock) l l l h h data input l l l h x data output x x x x h x during read(busy) on the devices x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect xxhxx 0v/v cc (2) stand-by note : 1.typical program time is defined as the time within which more than 50% of the whole pages are programmed at vcc of 3.3v an d 25?c KBE00F005A-D411 mcp memory june 2005 15 revision 1.0 ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us. 2. tbd means "to be determinded". parameter symbol min max unit data transfer from cell to register t r -15 s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 25 - ns we high to busy t wb - 100 ns read cycle time t rc 50 - ns re access time t rea -30ns ce access time t cea -45ns re high to output hi-z t rhz -30ns ce high to output hi-z t chz -20ns re or ce high to output hold t oh 15 - ns re high hold time t reh 15 - ns output hi-z to re low t ir 0-ns we high to re low t whr 60 - ns device resetting time(read/program/erase) t rst - 5/10/500 (1) s ac timing characteristics for command / address / data input note : 1. if tcs is set less than 10ns, twp must be minimum 35ns, otherwise, twp may be minimum 25ns. parameter symbol min max unit cle set-up time t cls 0- ns cle hold time t clh 10 - ns ce setup time t cs 0.- ns ce hold time t ch 10 - ns we pulse width t wp 25 (1) -ns ale setup time t als 0- ns ale hold time t alh 10 - ns data setup time t ds 20 - ns data hold time t dh 10 - ns write cycle time t wc 50 - ns we high hold time t wh 15 - ns KBE00F005A-D411 mcp memory june 2005 16 revision 1.0 nand flash technical notes identifying initial invalid block(s) initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is so call ed as the initial invalid block information. devices with init ial invalid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial i nvalid block(s) does not affect the performance of valid block(s) becau se it is isolated from the bit line and the common source line by a select transistor. the system design must be able to mask out the initial invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require error correction up to 1k program/erase cycle s. all device locations are erased(ffh) except locations where the in itial invalid block(s) information is written prior to shippi ng. the initial invalid block(s) status is defined by the 6th byte in the spare area. samsung makes sure that either the 1st or 2nd pag e of every initial invalid block has non-ffh data at the column addre ss of 517. since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. therefore, t he system must be able to recog nize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following sug- gested flow chart(figure 4). any intentional erasure of the initial invalid block information is prohibited. * check "ffh" at the column address 517 figure 4. flow chart to create initial invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no initial invalid block(s) table of the 1st and 2nd page in the block KBE00F005A-D411 mcp memory june 2005 17 revision 1.0 nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes error in write or read operation within its life time, additional invalid blocks may develop with nand flash memory. refer to the qualification report for the b lock failure rate.the following possible failure modes should be consid ered to implement a highly reliable system. in the case of st atus read failure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current tar get data and copying the rest of the replac ed block. in case of read, ecc must be employed. to improve the efficiency of memory space, it is re commended that the read failure due to single bit error should be reclaimed by ecc without any block replacement. the block failur e ratein the qualification report does not include those recla imed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection : if program operation r esults in an error, map out the block includin g the page in error and copy the * target data to another block. KBE00F005A-D411 mcp memory june 2005 18 revision 1.0 erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation resu lts in an error, map out the failing block an d replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes block replacement nand flash technical notes (continued) when the error happens with page "a" of block "a", try to write the data into another block "b" from an exter- nal buffer. then, prevent further system access to block "a" (by creating a "invalid block" table or other appropriate scheme.) buffer memory error occurs block a block b page a KBE00F005A-D411 mcp memory june 2005 19 revision 1.0 samsung nand flash has three address pointer commands as a subs titute for the two most significant column addresses. ?00h? command sets the pointer to ?a? area(0~255byte), ?01h? command se ts the pointer to ?b? area(256~511byte), and ?50h? command set s the pointer to ?c? area(512~527byte). with these commands, t he starting column address can be set to any of a whole page(0~527byte). ?00h? or ?50h? is sustained until another addr ess pointer command is inputted. ?01h? command, however, is effe ctive only for one operation. after any operation of read, program, erase, reset, power_up is executed once with ?01h? command, the address pointer returns to ?a? area by itself. to program data starting from ?a? or ?c? area, ?00h? or ?50h? command must be in putted before ?80h? command is written. a complete read operation prior to ?80h? command is not necessary. to program data starting fr om ?b? area, ?01h? command must be inputted right before ?80h? command is written. 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 01h (2) command input sequence for programming ?b? area address / data input 80h 10h 01h 80h 10h address / data input ?b?, ?c? area can be programmed. it depends on how many data are inputted. ?01h? command must be rewritten before every program operation the address pointer is set to ?b? area(256~511), and will be reset to ?a? area after every program operation is executed. 50h (3) command input sequence for programming ?c? area address / data input 80h 10h 50h 80h 10h address / data input only ?c? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?c? area(512~527), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b?,?c? area can be programmed. pointer operation table 2. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) "a" area 256 byte (00h plane) "b" area (01h plane) "c" area (50h plane) 256 byte 16 byte "a" "b" "c" internal page register pointer select commnad (00h, 01h, 50h) pointer figure 5. block diagram of pointer operation KBE00F005A-D411 mcp memory june 2005 20 revision 1.0 system interface using ce don?t-care. ce we t wp t ch t cs start add.(4cycle) 80h data input ce cle ale we i/o x data input ce don?t-care 10h for an easier system interface, ce may be inactive during the data-loading or sequential data-reading as shown below. the internal 528byte page registers are utilized as separate buffers for this operation and the system design gets more flexible. in additio n, for voice or audio applications which use slow cycle ti me on the order of u-seconds, de-activating ce during the data-loading and read- ing would provide significant savings in power consumption. start add.(4cycle) 00h ce cle ale we i/o x data output(sequential) ce don?t-care r/b t r re t cea out t rea ce re i/o x figure 6. program operation with ce don?t-care. figure 7. read operation with ce don?t-care. KBE00F005A-D411 mcp memory june 2005 21 revision 1.0 command latch cycle ce we cle ale i/o 0 ~ 7 command address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh ce we cle ale i/o 0 ~ 7 a 0 ~a 7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh a 9 ~a 16 t wc t wp t ds t dh t alh t als t wh a 17 ~a 24 t wc t wp t ds t dh t alh t als t wh t alh a 25,, a 26 t ds t dh t wp i/o data i/ox data in/out i/o 0 ~ i/o 7 ~528byte KBE00F005A-D411 mcp memory june 2005 22 revision 1.0 input data latch cycle ce cle we i/o 0 ~ 7 din 0 din 1 din 511 ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp serial access cycle after read (cle=l, we =h, ale=l) re ce r/b dout dout dout t rc t rea t rr t oh t rea t reh t rea t oh t rhz* notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. i/ox t chz* t rhz* KBE00F005A-D411 mcp memory june 2005 23 revision 1.0 t oh t oh read1 operation (read one page) ce cle r/b i/o 0 ~ 7 we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 column address page(row) address t wb t ar2 t r t rc t rhz t rr t chz dout 527 t wc a 25, a 26 status read cycle ce we cle re i/o x 70h status output t clr t clh t cs t wp t ch t ds t dh t rea t ir t oh t oh t whr t cea t cls t chz t rhz KBE00F005A-D411 mcp memory june 2005 24 revision 1.0 read1 operation (intercepted by ce ) ce cle r/b i/o 0 ~ 7 we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 page(row) address address column t wb t ar t chz t r t rr t rc read2 operation (read one page) ce cle r/b i/o 0 ~ 7 we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout dout 527 m address 511+m t ar t r t wb t rr a 0 ~a 3 : valid address a 4 ~a 7 : don t care a 25, a 26 a 25, a 26 selected row start address m 512 16 KBE00F005A-D411 mcp memory june 2005 25 revision 1.0 page program operation ce cle r/b i/o 0 ~ 7 we ale re 80h 70h i/o 0 din n din 10h 527 a 0 ~ a 7 a 17 ~ a 24 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc a 25, a 26 block erase operation (erase one block) ce cle r/b i/o 0 ~ 7 we ale re 60h a 17 ~ a 24 a 9 ~ a 16 auto block erase setup command erase command read status command i/o 0 =1 error in erase doh 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase page(row) address t wc a 25, a 26 KBE00F005A-D411 mcp memory june 2005 26 revision 1.0 multi-plane page program operation ce cle r/b i/o 0~7 we ale re 80h din n din 11h 527 a 0 ~ a 7 a 17 ~ a 24 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data serial input program max. three times repeatable tdbsy twb twc a 25 command last plane input & program t dbsy : typ. 1us max. 10us (dummy) din n din 10h 527 a 0 ~ a 7 a 17 ~ a 24 a 9 ~ a 16 tprog twb a 25 ,a 26 i/o 80h a 0 ~ a 7 & a 9 ~ a 26 i/o 0 ~ 7 r/b 528 byte data address & data input 11h 80h address & data input 11h 80h address & data input 11h 80h address & data input 10h ex.) four-plane page program into plane 0~3 or plane 4~7 t dbsy t dbsy t dbsy t prog program confirm command (true) 80h 71h 71h read multi-plane status command ,a 26 a 0 ~ a 7 & a 9 ~ a 26 528 byte data a 0 ~ a 7 & a 9 ~ a 26 528 byte data a 0 ~ a 7 & a 9 ~ a 26 528 byte data KBE00F005A-D411 mcp memory june 2005 27 revision 1.0 multi-plane block erase operation into plane 0~3 or plane 4~7 block erase setup command erase confirm command read multi-plane status command max. 4 times repeatable 60h a 9 ~ a 26 i/o 0 ~ 7 r/b address 60h address 60h address 60h address d0h 71h t bers * for multi-plane erase operation, block address to be erased should be repeated before "d0h" command. ex.) four-plane block erase operation ce cle r/b i/o 0 ~ 7 we ale re 60h a 17 ~ a 24 a 9 ~ a 16 doh 71h i/o 0 busy t wb t bers page(row) address t wc a 25, a 26 KBE00F005A-D411 mcp memory june 2005 28 revision 1.0 read id operation ce cle i/o 0 ~ 7 we ale re 90h read id command maker code 00h ech t read address. 1cycle a5h c0h multi plane code id defintition table 90 id : access command = 90h value description 1 st byte 2 nd byte 3 rd byte 4 th byte ech 79h a5h c0h maker code device code must be don?t -cared supports multi plane operation (must be don?t-cared for 1.8v device) 79h device code KBE00F005A-D411 mcp memory june 2005 29 revision 1.0 copy-back program operation ce cle r/b i/o 0 ~ 7 we ale re 00h 70h i/o 0 8ah a 0 ~a 7 a 17 ~a 24 a 9 ~a 16 column address page(row) address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc a 0 ~a 7 a 17 ~a 24 a 9 ~a 16 column address page(row) address busy t wb t r busy a 25, a 26 a 25, a 26 10h copy-back data input command KBE00F005A-D411 mcp memory june 2005 30 revision 1.0 device operation page read upon initial device power up, the device defaults to read1 mode. this operation is also initiate d by writing 00h to the command reg- ister along with four address cycles. once the command is latched, it does not need to be written for the following page read o pera- tion. three types of operations are available : random read, serial page read and sequential row read. the random read mode is enabled when the page address is change d. the 528 bytes of data within the selected page are trans- ferred to the data registers in less than 15 s(t r ). the system controller can detect the completion of this data transfer(tr) by analyz- ing the output of r/b pin. once the data in a page is loaded into the register s, they may be read out in 50ns cycle time by sequentially pulsing re . high to low transitions of the re clock output the data stating from the selected column address up to the last column address. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area of bytes 512 to 527 may be selectively accessed by writing the read2 command. addresses a 0 to a 3 set the starting address of the spare area while addresses a 4 to a 7 are ignored. unless the operation is aborted, the page address is automatically incremented for sequential row read as in read1 operation and spare sixteen bytes of each page may be sequentially read. the read1 com- mand(00h/01h) is needed to move the pointer back to the main area. figures 9 to 12 show typical sequence and timings for each read operation. KBE00F005A-D411 mcp memory june 2005 31 revision 1.0 figure 8. read1 operation start add.(4cycle) 00h a 0 ~ a 7 & a 9 ~ a 26 data output(sequential) (00h command) data field spare field ce cle ale r/b we i/o 0 ~ 7 re t r * after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. (01h command)* data field spare field 1st half array 2st half array 1st half array 2st half array KBE00F005A-D411 mcp memory june 2005 32 revision 1.0 figure 9. read2 operation 50h a 0 ~ a 3 & a 9 ~ a 26 data output(sequential) spare field ce cle ale r/b we data field spare field start add.(4cycle) (a 4 ~ a 7 : don t care) i/o 0 ~ 7 re t r 1st half array 2nd half array KBE00F005A-D411 mcp memory june 2005 33 revision 1.0 page program the device is programmed basically on a page basis, but it does allo w multiple partial page programing of a byte or consecutive bytes up to 528, in a single page program cycle. the number of consecut ive partial page programming operation within the same page wi th- out an intervening erase operation must not exceed 1 for main array and 2 for spare array. the addressing may be done in any ra n- dom order in a block. a page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loa ded into the page register, followed by a non-volatile programming pe riod where the loaded data is programmed into the appropriate cell. serial data loading can be started from 2nd half array by moving pointer. about the pointer operat ion, please refer to the atta ched technical notes. the serial data loading period begins by inputting the serial data input command(80h), followed by the four cycle address input and then serial data loading. the bytes other th an those to be programmed do not need to be loaded.the page program confirm com- mand(10h) initiates the programming process. writing 10h alone wi thout previously entering the seri al data will not initiate th e pro- gramming process. the internal write stat e control automatically executes the algorit hms and timings necessary for program and verify, thereby freeing the system controller for other tasks. on ce the program process starts, the read status register comman d may be entered, with re and ce low, to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is co mplete, the write status bit(i/o 0) may be checked(figure 10 ). the internal write verify detects only errors for "1"s that are not successfully prog rammed to "0"s. the command register remai ns in read status command mode until another valid command is written to the command register. figure 10. program & read status operation 80h a 0 ~ a 7 & a 9 ~ a 26 i/o 0 ~ 7 r/b address & data input i/o 0 pass 528 byte data 10h 70h fail t prog figure 11. block erase operation block erase the erase operation is done on a block(16k byte) basis. block ad dress loading is accomplished in three cycles initiated by an e rase setup command(60h). only address a 14 to a 26 is valid while a 9 to a 13 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. when the erase operation is completed, t he write status bit(i/o 0) may be che cked. figure 11 details the sequence. 60h block add. : a 14 ~ a 26 i/o 0 ~ 7 r/b address input(3cycle) i/o 0 pass d0h 70h fail t bers KBE00F005A-D411 mcp memory june 2005 34 revision 1.0 multi-plane page program into plane 0~3 or plane 4~7 multi-plane page program is an extension of page program, which is executed for a single plane with 528 byte page registers. si nce the device is equipped with eight memory planes, activating the four sets of 528 byte page registers into plane 0~3 or plane 4~ 7 enables a simultaneous programming of four pages. pa rtial activation of four planes is also permitted. after writing the first set of data up to 528 byte into the selected page register, dummy page program command (11h) instead of actual page program (10h) is inputted to finish data-loading of the current plane and move to the next plane. since no programm ing process is involved, r/b remains in busy state for a short period of time(tdbsy). read status command (standard 70h or alternate 71h) may be issued to find out when the device returns to ready state by polling the ready/busy status bit(i/o 6). then the nex t set of data for one of the other planes is in putted with the same command and address sequences. after inputting data for the last plane, actual true page program (10h) instead of dummy page progr am command (11h) must be followed to start the programming pro- cess. the operation of r/b and read status is the same as that of page progra m. since maximum four pages into plane 0~3 or plane 4~7 are programmed simultaneously, pass/fail status is avail able for each page when the program operation completes. the extended status bits (i/o1 through i/o 4) are checked by inputt ing the read multi-plane status register. status bit of i/o 0 is set to "1" when any of the pages fails. multi-plane page program with "01h" point er is not supported, thus prohibited. figure 12. four-plane page program 80h 11h 80h 11h 80h 11h 80h 10h data input plane 0 plane 1 plane 2 plane 3 (1024 block) (1024 block) (1024 block) (1024 block) block 0 block 4 block 4092 block 4088 block 1 block 5 block 4093 block 4089 block 2 block 6 block 4094 block 4090 block 3 block 7 block 4095 block 4091 80h a 0 ~ a 7 & a 9 ~ a 26 i/o 0 ~ 7 r/b 528 byte data address & data input 11h 80h address & data input 11h 80h address & data input 11h 80h address & data input 10h t dbsy t dbsy t dbsy t prog 71h a 0 ~ a 7 & a 9 ~ a 26 528 byte data a 0 ~ a 7 & a 9 ~ a 26 528 byte data a 0 ~ a 7 & a 9 ~ a 26 528 byte data KBE00F005A-D411 mcp memory june 2005 35 revision 1.0 restirction in addressing with multi plane page program while any block in each plane may be addressable for multi-plane page program, the four least significant addresses(a9-a13) for the selected pages at one operation must be the same. figure 13 shows an example where 2nd page of each addressed block is selected for four planes. however, any arbitrary sequence is allowed in addressing multiple planes as shown in figure17. 80h plane 2 11h 80h 11h 80h 11h 80h 10h plane 0 plane3 plane 1 plane 0 plane 1 plane 2 plane 3 (1024 block) (1024 block) (1024 block) (1024 block) page 0 page 1 page 31 page 30 block 0 page 0 page 1 page 31 page 30 block 1 page 0 page 1 page 31 page 30 block 2 page 0 page 1 page 31 page 30 block 3 figure 15. multi-plane page program & read status operation 80h a 0 ~ a 7 & a 9 ~ a 26 i/o 0 ~ 7 r/b address & data input i/o pass 528 byte data 10h 71h fail t prog last plane input multi-plane block erase into plane 0~3 or plane 4~7 basic concept of multi-plane block erase operation is identical to that of multi-plane page program. up to four blocks, one fro m each plane can be simultaneously erased. standard block erase command sequences (block erase setup command followed by three address cycles) may be repeated up to four times for erasing up to four blocks. only one block should be selected from each pla ne. the erase confirm command initiates the actual erasing process. the completion is detected by analyzing r/b pin or ready/busy status (i/o 6). upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(i/o 1 through i/o 4). figure 16. four block erase operation 60h a 0 ~ a 7 & a 9 ~ a 26 i/o 0 ~ 7 r/b address 60h 60h 60h d0h 71h i/o pass fail t bers (3 cycle) address (3 cycle) address (3 cycle) address (3 cycle) figure 13. multi-plane program & read status operation figure 14. addressing multiple planes KBE00F005A-D411 mcp memory june 2005 36 revision 1.0 copy-back program figure 17. one page copy-back program operation 00h a 0 ~ a 7 & a 9 ~ a 26 i/o 0 ~ 7 r/b add.(4cycles) i/o 0 pass 8ah 70h fail t prog a 0 ~ a 7 & a 9 ~ a 26 add.(4cycles) t r source address destination address the copy-back program is configured to quickly and efficiently re write data stored in one page within the plane to another page within the same plane without utilizing an external memory. since t he time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. the benefit is especially obvious when a por tion of a block is updated and the res t of the block also need to be copied to the newly assigned free blo ck. the operation for performing a copy-back program is a sequen tial execution of page-read without burst-readi ng cycle and copying-program with the addre ss of destination page. a normal read oper a- tion with "00h" command and the address of the source page moves the whole 528byte data into the internal buffer. as soon as th e device returns to ready state, page-copy data-input command (8ah ) with the address cycles of destination page followed may be written. the program confirm command (10h) is required to ac tually begin the programming operation. copy-back program opera- tion is allowed only within the same memory plane. once the copy-back program is finished, any additional partial page program- ming into the copied pages is prohibited bef ore erase. a14, a15 and a26 must be the same between source and target page. figure20 shows the command sequence for single plane operation. "when there is a program-failure at copy-back operation, error is reported by pass/fail status. but if the soure page has a bit error for charge loss , accumulated copy-back operations could also accumulate bit errors. for this reason, two bit ecc is r ecommended for copy -back operation. " 10h KBE00F005A-D411 mcp memory june 2005 37 revision 1.0 multi-plane copy-back program multi-plane copy-back program is an extension of one page copy-b ack program into four plane operation. since the device is equipped with four memory planes, activating the four sets of 528 bytes page registers enables a simultaneous multi-plane copy- back programming of four pages. partial acti vation of four planes is also permitted. first, normal read operation with the "00h"command and address of the source page moves the whole 528 byte data into internal page buffers. any further read operation for transferring the addressed pages to the corresponding page register must be execut ed with "03h" command instead of "00h" command. any plane may be sele cted without regard to "00h" or " 03h". up to four planes may be addressed. data moved into the internal page registers are loaded into the destination plane addresses. after the input of c om- mand sequences for reading the source pages, the same proce dure as multi-plane page programming except for a replacement address command with "8ah" is executed. since no programming proc ess is involved during data loading at the destination plane address , r/b remains in busy state for a short period of time(tdbsy). re ad status command (standard 70h or alternate 71h) may be issued to find out when the device returns to ready state by polling the ready/busy status bit(i/o 6). after inputting data for the last plane, actual true page program (10h) instead of dummy page program command (11h) must be followed to start the programming process. the operation of r/b and read status is the same as that of page program. since maximum four pages are programmed simultaneously, pass/fail status is available for each page when the program operation completes. no pointer operation is suppo rted with multi-plane copy-back program. once the multi-plane copy-back program is finished, any additional partial page pro- gramming into the copied pages is pr ohibited before erase once the multi- plane copy-back program is finished. figure 18. four-plane copy-back program 8ah 11h 8ah 11h 8ah 11h 8ah 10h destination plane 0 plane 1 plane 2 plane 3 (1024 block) (1024 block) (1024 block) (1024 block) block 0 block 4 block 4092 block 4088 block 1 block 5 block 4093 block 4089 block 2 block 6 block 4094 block 4090 block 3 block 7 block 4095 block 4091 00h 03h 03h 03h source plane 0 plane 1 plane 2 plane 3 (1024 block) (1024 block) (1024 block) (1024 block) block 4 block 4092 block 4088 block 5 block 4093 block 2 block 6 block 4094 block 4090 block 3 block 7 block 4095 block 4091 address address input input block 0 block 1 block 4089 block 4089 max three times repeatable max three times repeatable KBE00F005A-D411 mcp memory june 2005 38 revision 1.0 00h a 0 ~ a 7 & a 9 ~ a 25 i/o x r/b source address add.(4cyc.) 03h figure 19. four-plane copy-back page program (continued) t r t dbsy a 0 ~ a 7 & a 9 ~ a 25 destination address add.(4cyc.) 11h 71h a 0 ~ a 7 & a 9 ~ a 25 source address add.( 4cyc.) 8ah 03h a 0 ~ a 7 & a 9 ~ a 25 source address add.( 4cyc.) a 0 ~ a 7 & a 9 ~ a 25 destination address add.(4cyc.) 11h 8ah a 0 ~ a 7 & a 9 ~ a 25 destination address add.(4cyc.) 10h 8ah t r t prog t dbsy max. 4 times ( 4 cycle source address input) repeatable max. 4 times (4 cycle destination address input) repeatable tr : normal read busy tdbsy : typical 1us, max 10us t r KBE00F005A-D411 mcp memory june 2005 39 revision 1.0 read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. afte r writing 70h command to the command register, a read cycle outpu ts the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 4 for specific status register definitions. the command register remains in status read mode until further commands are issued to i t. therefore, if the status regi ster is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle. for read status of multi plane program/erase, the read multi- plane status command(71h) should be used to find out whether multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. the pass/fail status data must be checked only in the ready conditi on after the completion of multi-plane program or erase operatio n. table4. read staus register definition note : 1. i/o 0 describes combined pass/fail condition for all planes. if any of the selected multiple pages/blocks fails in program/ erase operation, it sets "fail" flag. 2. the pass/fail status applies only to the corresponding plane. i/o no. status definition by 70h command definition by 71h command i/o 0 total pass/fail pass : "0" fail : "1" pass : "0" (1) fail : "1" i/o 1 plane 0 pass/fail must be don?t -cared pass : "0" (2) fail : "1" i/o 2 plane 1 pass/fail must be don?t -cared pass : "0" (2) fail : "1" i/o 3 plane 2 pass/fail must be don?t -cared pass : "0" (2) fail : "1" i/o 4 plane 3 pass/fail must be don?t -cared pass : "0" (2) fail : "1" i/o 5 reserved must be don?t -cared must be don?t-cared i/o 6 device operation busy : "0" read y : "1" busy : "0" ready : "1" i/o 7 write protect protected : "0" not protect ed : "1" protected : "0" not protected : "1" KBE00F005A-D411 mcp memory june 2005 40 revision 1.0 figure 20. read id operation 1 ce cle i/o 0 ~ 7 ale re we 90h 00h ech address. 1cycle maker code t cea t ar t rea read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inp ut of 00h. four read cycles sequentially output the manufacture code(ech), and the devic e code*, reserved(a5h), multi plane operation code(c0h) respectively. a5h must be don?t-cared. c0h means that device supports multi plane operation but must be don?t-cared f or 1.8v device. the command register remains in read id mode until further commands are issued to it. figure 20 shows the operatio n sequence. a5h c0h multi-plane code t whr 79h device code KBE00F005A-D411 mcp memory june 2005 41 revision 1.0 figure 21. reset operation reset the device offers a reset feature, execut ed by writing ffh to the command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 5 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted by the command register. the r/b pin transitions to low for trst after the reset command is wri tten. refer to figure 21 below. table5. device status after power-up after reset operation mode read 1 waiting for next command ffh i/o 0 ~ 7 r/b t rst KBE00F005A-D411 mcp memory june 2005 42 revision 1.0 ready/busy the device has a r/b output that provides a hardware method of indicati ng the completion of a page program, erase and random read completion. the r/b pin is normally high but transitions to low after pr ogram or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the internal controller has finished the operation . the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull- up resistor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(fig 25). its value can be determined by the following guidance. v cc r/b open drain output device gnd rp figure 22. rp vs tr ,tf & rp vs ibusy ibusy busy ready vcc voh tf tr vol c l 0.4v, v oh : vcc q -0.4v tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 2.7v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 2.3 2.3 2.3 2.3 2.3 1.1 0.75 0.55 where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maximum permissible limit of tr rp(min, 2.7v part) = v cc (max.) - v ol (max.) i ol + i l = 2.5v 3ma + i l KBE00F005A-D411 mcp memory june 2005 43 revision 1.0 the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 1.8v. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down and recovery time of minimum 10 s is required before internal circuit gets ready for any com- mand sequences as shown in figure 23. the two step command s equence for program/erase provides additional software protec- tion. figure 23. ac waveforms for power transition v cc wp high we data protection & power up sequence 10 s ~ 2.0v ~ 2.0v KBE00F005A-D411 mcp memory june 2005 44 revision 1.0 mobile sdram ddp f-die 512mb(16mb x 32) KBE00F005A-D411 mcp memory june 2005 45 revision 1.0 functional block diagram 8mx32 8mx32 dq0~dq31 a0~a12, ba0, ba1 clk, /cas, /ras, /we, dqm, cke /cs1 /cs0 KBE00F005A-D411 mcp memory june 2005 46 revision 1.0 dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 to 85 c) notes : 1. vih (max) = 2.2v ac.the overshoot voltage duration is 3ns. 2. vil (min) = -1.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v vin vddq. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. dout is disabled, 0v vout vddq. parameter symbol min typ max unit note supply voltage v dd 1.7 1.8 1.95 v v ddq 1.7 1.8 1.95 v input logic high voltage v ih 0.8 x v ddq 1.8 v ddq + 0.3 v 1 input logic low voltage v il -0.3 0 0.3 v 2 output logic high voltage v oh v ddq -0.2 - - v i oh = -0.1ma output logic low voltage v ol - - 0.2 v i ol = 0.1ma input leakage current i li -2 - 2 ua 3 capacitance (v dd = 1.8v, t a = 23 c, f = 1mhz, v ref =0.9v 50 mv) pin symbol min max unit note clock c clk 2.5 6 pf cs c in 1.5 3 pf ras , cas , we , cke c in 2.5 6 pf dqm c in 2.5 6 pf address c add 2.5 6 pf dq 0 ~ dq 31 c out 5 10 pf absolute maximum ratings notes: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. parameter symbol value unit voltage on any pin relative to v ss v in , v out -1.0 ~ 2.6 v voltage on v dd supply relative to v ss v dd , v ddq -1.0 ~ 2.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.0 w short circuit current i os 50 ma KBE00F005A-D411 mcp memory june 2005 47 revision 1.0 dc characteristics recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 to 85 c) notes: 1. measured with outputs open. 2. refresh period is 64ms. 3. unless otherwise noted, input swing ievei is cmos(vih /vil=vddq/vssq). 4. measued with assumption that one of the 2 die should be in a state of precharge standby in non power-down mode. parameter symbol test condition KBE00F005A-D411 111mhz@cl3 unit note operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) i o = 0 ma 50 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 0.6 ma i cc2 ps cke & clk v il (max), t cc = 0.6 precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 20 ma i cc2 ns cke v ih (min), clk v il (max), t cc = input signals are stable 2 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 6 ma i cc3 ps cke & clk v il (max), t cc = 2 active standby current in non power-down mode (one bank active) i cc3 n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 30 ma i cc3 ns cke v ih (min), clk v il (max), t cc = input signals are stable 6 ma operating current (burst mode) i cc 4 i o = 0 ma page burst 4banks activated t ccd = 2clks 90 ma 1 refresh current i cc 5 t arfc t arfc (min) 70 ma 2 self refresh current i cc 6 cke 0.2v tcsr range max 40 max 85 c full array 300 800 ua 1/2 of full array 240 600 1/4 of full array 200 500 KBE00F005A-D411 mcp memory june 2005 48 revision 1.0 1.8v 13.9k ? 10.6k ? output 20pf voh (dc) = vddq - 0.2v, ioh = -0.1ma vol (dc) = 0.2v, iol = 0.1ma vtt=0.5 x vddq 50 ? output 20pf z0=50 ? figure 2. ac output load circuit figure 1. dc output load circuit ac operating test conditions (v dd = 1.7v 1.95v, t a = -25 to 85 c) parameter value unit ac input levels (vih/vil) 0.9 x v ddq / 0.2 v input timing measurement reference level 0.5 x v ddq v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 0.5 x v ddq v output load condition see figure 2 KBE00F005A-D411 mcp memory june 2005 49 revision 1.0 operating ac parameter (ac operating conditions unless otherwise noted) notes: 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then roundi ng off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. parameter symbol KBE00F005A-D411 111mhz@cl3 unit note row active to row active delay t rrd (min) 18 ns 1 ras to cas delay t rcd (min) 27 ns 1 row precharge time t rp (min) 27 ns 1 row active time t ras (min) 50 ns 1 t ras (max) 100 us row cycle time t rc (min) 77 ns 1 last data in to row precharge t rdl (min) 15 ns 2 last data in to active delay t dal (min) trdl + trp - last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 auto refresh cycle time t arfc (min) 80 ns exit self refresh to active command t srfx (min) 120 ns col. address to col. address delay t ccd (min) 1 clk 3 number of valid output data cas latency=3 2 ea 4 number of valid output data cas latency=2 1 number of valid output data cas latency=1 0 KBE00F005A-D411 mcp memory june 2005 50 revision 1.0 ac characteristics (ac operating conditions unless otherwise noted) notes : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, parameter symbol KBE00F005A-D411 111mhz@cl3 unit note min max clk cycle time cas latency=3 t cc 9 1000 ns 1 cas latency=2 t cc 15 cas latency=1 t cc 25 clk to valid output delay cas latency=3 t sac 7 ns 1,2 cas latency=2 t sac 10 cas latency=1 t sac 20 output data hold time cas latency=3 t oh 2.0 ns 2 cas latency=2 t oh 2.0 cas latency=1 t oh 2.0 clk high pulse width t ch 3.0 ns 3 clk low pulse width t cl 3.0 ns 3 input setup time t ss 2.0 ns 3 input hold time t sh 1.5 ns 3 clk to output in low-z t slz 1 ns 2 clk to output in hi-z cas latency=3 t shz 7 ns cas latency=2 10 cas latency=1 20 KBE00F005A-D411 mcp memory june 2005 51 revision 1.0 simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) notes : 1. op code : operand code a0 ~ a12 & ba0 ~ ba1 : program keys. (@mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are the same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. partial self refresh can be issued only after setting partial self refresh mode of emrs. 4. ba0 ~ ba1 : bank select addresses. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at the positive going edge of clk masks the data-in at that same clk in write operation (write dqm latency is 0), but in read operation, it makes the data-out hi-z state after 2 clk cycles. (read dqm latency is 2). command cken-1 cken cs ras cas we dqm ba 0,1 a10/ap a12,a11, a9 ~ a0 note register mode register set h x l l l l x op code 1, 2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a0~a7) 4 auto precharge enable h 4, 5 write & column address auto precharge disable h x l h l l x v l column address (a0~a7) 4 auto precharge enable h 4, 5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h x v x 7 no operation command h x h x x x x x l h h h KBE00F005A-D411 mcp memory june 2005 52 revision 1.0 register programmed with extended mrs address ba1 ba0 a12 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function mode select rfu *1 ds rfu *1 pasr normal mrs mode test mode cas latency burst type burst length a8 a7 type a6 a5 a4 latency a3 type a2 a1 a0 bt=0 bt=1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 1 0 1 reserved 0 0 1 1 1 interleave 0 0 1 2 2 1 0 reserved 0 1 0 2 mode select 0 1 0 4 4 1 1 reserved 0 1 1 3 ba1 ba0 mode 0 1 1 8 8 write burst length 1 0 0 reserved 0 0 setting for nor- mal mrs 1 0 0 reserved reserved a9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 reserved reserved 1 single bit 1 1 1 reserved 1 1 1 full page reserved register programmed with normal mrs address ba0 ~ ba1 a12 ~ a10/ap a9 *2 a8 a7 a6 a5 a4 a3 a2 a1 a0 function "0" setting for normal mrs rfu *1 w.b.l test mode cas latency bt burst length a. mode register field table to program modes notes: 1.rfu(reserved for future use) should stay "0" during mrs cycle. 2.if a9 is high during mrs cycle, "burst read single bit write" function will be enabled. mode select driver strength pasr ba1 ba0 mode a6 a5 driver strength a2 a1 a0 size of refreshed area 0 0 normal mrs 0 0 full 0 0 0 full array 0 1 reserved 0 1 1/2 0 0 1 1/2 of full array 1 0 emrs for mobile sdram 1 0 1/4 0 1 0 1/4 of full array 1 1 reserved 1 1 1/8 0 1 1 reserved reserved address 1 0 0 reserved a12~a10/ap a9 a8 a7 a4 a3 1 0 1 reserved 0 0 0 0 0 0 1 1 0 reserved 1 1 1 reserved emrs for pasr(partial array self ref.) & ds(driver strength) full page length x32 : 512mb(512) KBE00F005A-D411 mcp memory june 2005 53 revision 1.0 1. in order to save power consumption, mobile sdram has pasr option. 2. mobile sdram supports 3 kinds of pasr in self refres h mode : full array, 1/2 of fu ll array, 1/4 of full array ba1=0 - full array - 1/2 array - 1/4 array partial self refresh area ba0=0 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 ba1=1 ba0=1 ba1=1 ba0=0 ba1=0 ba0=1 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 partial array self refresh b. power up sequence note : 1. in order to save power consumption, mobile-sdram includes t he internal temperature sensor and control units to control the self refresh cycle automatically accordin g to the two temperature range ; max. 40 c, max. 85 c. 2. if the emrs for external tcsr is issued by the controller, this emrs code for tcsr is ignored. temperature range self refresh current (icc 6) unit full array 1/2 of full array 1/4 of full array max. 40 c 300 240 200 ua max. 85 c 800 600 500 internal temperature compensated self refresh (tcsr) 1. apply power and attempt to maintain cke at a high state and all other inputs may be undefined. - apply vdd before or at the same time as vddq. 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. 6. issue a extended mode register set command to define ds or pasr operating type of the device after normal mrs. emrs cycle is not mandatory and the emrs command n eeds to be issued only when ds or pasr is used. the default state without emrs command issued is the half driver strength and full array refreshed. the device is now ready for the operation selected by emrs. for operating with ds or pasr , set ds or pasr mode in emrs setting stage. in order to adjust another mode in the state of ds or pasr mode, additional emrs set is required but power up sequence is not needed again at this time. in that case, all banks hav e to be in idle state prior to adjusting emrs set. KBE00F005A-D411 mcp memory june 2005 54 revision 1.0 c. burst sequence 1. burst length = 4 initial address sequential interleave a1 a0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 2. burst length = 8 initial address sequential interleave a2 a1 a0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 KBE00F005A-D411 mcp memory june 2005 55 revision 1.0 d. device operations bank addresses (ba0 ~ ba1) this sdram is organized as two chips which has four indepen- dent banks of 2,097,152 words x 32 bits memory arrays. the ba0 ~ ba1 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. the bank addresses ba0 ~ ba1 are latched at bank active, read, write, mode register set and precharge operations. address inputs (a0 ~ a12) the 21 address bits are required to decode the 8,388,608 word locations are multiplexed into 13 address input pins (a0 ~ a12). the 13 bit row addresses are latched along with ras and ba0 ~ ba1 during bank activate command. the 8 bit column addresses (a0 ~ a7) are latched along with cas , we and ba0 ~ ba1 during read or write command. addresses of 512mb clock (clk) the clock input is used as the reference for all sdram opera- tions. all operations are synchronized to the positive going edge of the clock. the clock transitions must be monotonic between v il and v ih . during operation with cke high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well q perform and icc specifications. clock enable (cke) the clock enable(cke) gates the clock onto sdram. if cke goes low synchronously with clock (set-up and hold time are the same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is fro- zen as long as the cke remains low. all other inputs are ignored from the next clock cycle after cke goes low. when all banks are in the idle state and cke goes low synchronously with clock, the sdram enters the power down mode from the next clock cycle. the sdram remains in the power down mode ignoring the other inputs as long as cke remains low. the power down exit is syn- chronous as the internal clock is suspended. when cke goes high at least "1clk + tss" before the high going edge of the clock, then the sdram becomes active from the same clock edge accepting all the input commands. nop and device deselect when ras , cas and we are high, the sdram performs no operation (nop). nop does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. the device deselect is also a nop and is entered by asserting cs high. cs high disables the command decoder so that ras , cas , we and all the address inputs are ignored. KBE00F005A-D411 mcp memory june 2005 56 revision 1.0 d. device operations (continued) dqm operation the dqm is used to mask input and output operations. it works similar to oe during read operation and inhibits writing during write operation. the read late ncy is two cycles from dqm and zero cycle for write, which means dqm masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. dqm operation is synchronous with the clock. the dqm signal is important during bu rst interruptions of write with read or precharge in the sdram. due to asynchronous nature of the internal write, the dqm operat ion is critical to avoid unwanted or incomplete writes when the complete burst write is not required. please refer to dqm timing diagram also. mode register set (mrs) the mode register stores the data for controlling the various operating modes of sdram. it programs the cas latency, burst type, burst length, test mode and various vendor specific options to make sdram useful for variety of different applications. the default value of the mode register is not defined, therefore the mode register must be written after power up to operate the sdram. the mode register is written by asserting low on cs , ras , cas and we (the sdram should be in active mode with cke already high prior to writin g the mode register). the state of address pins a0 ~ an and ba0 ~ ba1 in the same cycle as cs , ras , cas and we going low is the data written in the mode reg- ister. two clock cycles is required to complete the write in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during opera- tion as long as all banks are in the idle state. the mode register is divided into various fields depending on the fields of functions. the burst length field uses a0 ~ a2, burst type uses a3, cas latency (read latency from column address) use a4 ~ a6, vendor specific options or test mode use a7 ~ a8, a10/ap ~ an and ba0 ~ ba1. the write burst length is programmed using a9. a7 ~ a8, a10/ap ~ an and ba0 ~ ba1 must be set to low for normal sdram operation. refer to the table for specific codes for vari- ous burst length, burst type and cas latencies. extended mode register set (emrs) the extended mode register stores the data for selecting driver strength, partial self refresh or temperature compensated self refresh. emrs cycle is not mandatory and the emrs command needs to be issued only when ds or pasr is used. the default state without emrs command issued is half driver strength, and all 4 banks refreshed. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba1 ,low on ba0(the sdram should be in all bank precharge with cke already high prior to writing into the extended mode register). the state of address pins a0 ~ a12 in the same cycle as cs , ras , cas and we going low is written in the extended mode register. two clock cycles are required to complete the write operation in the extended mode register. the mode register con- tents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. a0 - a2 are used for partial self refresh , a5 - a6 are used for driver strength, "low" on ba1 and "high" on ba0 are used for emrs. all the other address pins except a0-a2, a5-a6 and ba1, ba0 must be set to low for proper emrs operation. refer to the table for specific codes. bank activate. the bank activate command is used to select a random row in an idle bank. by asserting low on ras and cs with desired row and bank address, a row access is init iated. the read or write opera- tion can occur after a time delay of t rcd (min) from the time of bank activation. t rcd is an internal timing parameter of sdram, therefore it is dependent on oper ating clock frequency. the mini- mum number of clock cycles required between bank activate and read or write command should be calculated by dividing t rcd (min) with cycle time of the clock and then rounding off the result to the next higher integer. KBE00F005A-D411 mcp memory june 2005 57 revision 1.0 d. device operations (continued) the sdram has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. also the noise generated during sensing of each bank of sdram is high, requiring some time for power supplies to recover before another bank can be sensed reliably. t rrd (min) specifies the minimum time required between activating different bank. the number of clock cycles required between different bank activation must be calculated similar to t rcd specification. the minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t ras (min). every sdram bank activate command must satisfy t ras (min) specification before a prechar ge command to that active bank can be asserted. the maximum time any bank can be in the active state is determined by t ras (max). the number of cycles for both t ras (min) and t ras (max) can be calculated similar to t rcd specification. burst read the burst read command is used to access burst of data on con- secutive clock cycles from an active row in an active bank. the burst read command is issued by asserting low on cs and cas with we being high on the positive edge of the clock. the bank must be active for at least t rcd (min) before the burst read com- mand is issued. the first output appears in cas latency number of clock cycles after the issue of burst read command. the burst length, burst sequence and laten cy from the burst read command is determined by the mode register which is already pro- grammed. the burst read can be initiated on any column address of the active row. the address wraps around if the initial address does not start from a boundary such that number of outputs from each i/o are equal to the burst length programmed in the mode register. the output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data out- put gapless. the burst read can be terminated by issuing another burst read or burst write in th e same bank or the other active bank or a precharge command to the same bank. the burst stop command is valid at every page burst length. burst write the burst write command is similar to burst read command and is used to write data into the sdram on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. by asserting low on cs , cas and we with valid col- umn address, a write burst is init iated. the data inputs are pro- vided for the initial address in the same clock cycle as the burst write command. the input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. the writing can be completed by issuing a burst read and dqm for blocking data inputs or burst write in the same or another active bank. the burst stop command is valid at every burst length. the write burst can also be terminated by using dqm for blocking data and procreating the bank t rdl after the last data input to be written into the active row. see dqm oper- ation also. all banks precharge all banks can be precharged at the same time by using pre- charge all command. asserting low on cs , ras , and we with high on a10/ap after all banks have satisfied t ras (min) require- ment, performs precharge on all banks. at the end of t rp after performing precharge to all the banks, all banks are in idle state. precharge the precharge operation is performed on an active bank by asserting low on cs , ras , we and a10/ap with valid ba0 ~ ba1 of the bank to be precharged. the precharge command can be asserted anytime after t ras (min) is satisfied from the bank active command in the desired bank. t rp is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing t rp with clock cycle time and rounding up to the next higher integer. care should be taken to make sure that burst write is completed or dqm is used to inhibit writing before precharge command is asserted. the maximum time any bank can be active is specified by t ras (max). therefore, each bank activate command. at the end of precharge, the bank enters the idle state and is ready to be activated again. entry to power down, auto refresh, self refresh and mode register set etc. is possible only when all banks are in idle state. KBE00F005A-D411 mcp memory june 2005 58 revision 1.0 d. device operations (continued) auto precharge the precharge operation can also be performed by using auto precharge. the sdram internally generates the timing to satisfy t ras (min) and "t rp " for the programmed burst length and cas latency. the auto precharge comm and is issued at the same time as burst read or burst write by asserting high on a10/ap. if burst read or burst write by asserting high on a10/ap, the bank is left active until a new command is asserted. once auto precharge command is given, no new commands are possible to that partic- ular bank until the bank achieves idle state. auto refresh the storage cells of 64mb, 128mb and 256mb sdram need to be refreshed every 64ms to maintain data. an auto refresh cycle accomplishes refresh of a single row of storage cells. the inter- nal counter increments automatically on every auto refresh cycle to refresh all the rows. an auto refresh command is issued by asserting low on cs , ras and cas with high on cke and we . the auto refresh command can only be asserted with all banks being in idle state and the device is not in power down mode (cke is high in the previous cycle). the time required to com- plete the auto refresh operation is specified by t rc (min). the min- imum number of clock cycles required can be calculated by driving t rc with clock cycle time and them rounding up to the next higher integer. the auto refresh command must be followed by nop's until the auto refresh operation is completed. all banks will be in the idle state at the end of auto refresh operation. the auto refresh is the preferred refresh mode when the sdram is being used for normal data transactions. the 64mb and 128mb sdram?s auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms. the 256mb and 512mb sdram?s auto refresh cycle can be performed once in 7.8us or a burst of 8192 auto refresh cycles once in 64ms. self refresh the self refresh is another refresh mode available in the sdram. the self refresh is the preferred refresh mode for data retention and low power operation of sdram. in self refresh mode, the sdram disables the internal clock and all the input buffers except cke. the refresh addressing and timing are inter- nally generated to reduce power consumption. the self refresh mode is entered from all banks idle state by asserting low on cs , ras , cas and cke with high on we . once the self refresh mode is entered, only cke state being low mat- ters, all the other inputs including the clock are ignored in order to remain in the self refresh mode. the self refresh is exited by re starting the external clock and then asserting high on cke. this must be followed by nop's for a minimum time of tsrfx before the sdram reaches idle state to begin normal operation. in case that the system uses burst auto refresh during normal operation, it is recommended to use burst 8192 auto refresh cycles for 256mb and 512mb, and burst 4096 auto refresh cycles for 128mb and 64mb immediately before entering self refresh mode and after exiting in self refresh mode. on the other hand, if the syst em uses the distributed auto refresh, the system only has to keep the refresh duty cycle. KBE00F005A-D411 mcp memory june 2005 59 revision 1.0 d hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z *note : 1. cke to clk disable/enable = 1clk. 2. dqm makes data out hi-z after 2clks which should masked by cke " l" 3. dqm masks both data-in and data-out. e. basic feature and function descriptions 1. clock suspend 2. dqm operation 1) clock suspended during write clk cmd cke internal clk dq(cl2) dq(cl3) wr d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 not written suspended dout 2) clock suspended during read (bl=4) clk cmd cke internal clk dq(cl2) dq(cl3) rd masked by cke q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 masked by cke 1) write mask (bl=4) 2) read mask (bl=4) clk cmd dqm dq(cl2) dq(cl3) clk cmd dqm dq(cl2) dq(cl3) wr masked by cke masked by cke d 0 d 1 d 3 d 0 d 1 d 3 rd q 0 q 2 q 3 q 1 q 2 q 3 dqm to data-in mask = 0 dqm to data-out mask = 2 3) dqm with clock suspended (full page read) *2 clk cmd cke dqm dq(cl2) dq(cl3) rd q 0 q 2 q 4 q 6 q 7 q 8 q 1 q 3 q 6 q 7 q 5 KBE00F005A-D411 mcp memory june 2005 60 revision 1.0 tccd *2 tccd *2 tcdl *3 tccd *2 tcdl *3 *note: 1. by " interrupt", it is meant to stop burst re ad/write by external command before the end of burst. by "cas interrupt", to stop bur st read/write by cas access ; read and write. 2. t ccd : cas to cas delay. (=1clk) 3. t cdl : last data in to new column address delay. (=1clk) dq(cl2) dq(cl3) 3. cas interrupt (i) 1) read interrupted by read (bl=4) *1 2) write interrupted by write (bl=2) clk cmd add rd rd ab 3) write interrupted by read (bl=2) qa 0 qb 0 qb 1 qb 1 qb 3 qa 0 qb 0 qb 1 qb 1 qb 3 clk cmd add dq wr wr ab da 0 db 0 db 1 clk cmd add dq(cl2) dq(cl3) wr rd ab da 0 qb 0 qb 1 da 0 qb 0 qb 1 KBE00F005A-D411 mcp memory june 2005 61 revision 1.0 *note: 1. to prevent bus contention, there should be at least one gap between data in and data out. hi-z hi-z *1 hi-z hi-z *1 hi-z 4. cas interrupt (ii) : read interrupted by write & dqm ii) cmd dqm (a) cl=2, bl=4 i) cmd dq clk dqm dq iii) cmd dqm dq iv) cmd dqm dq (b) cl=3, bl=4 clk i) cmd dqm dq ii) cmd dqm dq iii) cmd dqm dq iv) cmd dqm dq v) cmd dq dqm rd wr d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 rd wr q 0 d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 q 0 KBE00F005A-D411 mcp memory june 2005 62 revision 1.0 trdl =2clk tdal =trdl + trp *4 *note: 1. to prevent bus contention, dqm should be issued which makes at least one gap between data in and data out. 2. to inhibit invalid write, dqm should be issued. 3. this precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank pre- charge of four banks operation. trdl *1 1 2 *note: 1. samsung can support trdl=2clk . 2. number of valid output data after row precharge : 1, 2 for cas latency = 2, 3 respectively. 3. the row active command of the precharge bank can be issued after trp from this point. the new read/write command of other activated bank can be issued from this point. at burst read/write with auto precharge, cas interrupt of the same bank is illegal 4. tdal defined last data in to active delay. samsung can support tdal=trdl+ trp . auto precharge starts *3 *2 *3 *2 5. write interrupted by precharge & dqm 6. precharge 7. auto precharge 1) trdl = 2clk cmd dq clk dqm wr pre d 0 d 1 d 2 masked by dqm 1) normal write cmd dq clk bl=4 & trdl=2clk d 0 d 1 d 2 d 3 wr pre 2) normal read (bl=4) clk cmd dq(cl2) dq(cl3) rd pre q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 1) normal write (bl=4) clk cmd dq wr auto precharge starts@trdl=2clk *3 d 0 d 1 d 2 d 3 act 2) normal read (bl=4) clk cmd dq(cl2) dq(cl3) rd q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 KBE00F005A-D411 mcp memory june 2005 63 revision 1.0 *note: 1. samsung can support trdl=2clk. 2. tbdl : 1 clk ; last data in to burst stop delay. read or write burst stop command is valid at every burst length. 3. number of valid output data after row precharge or burst stop : 1, 2 for cas latency= 2, 3 respectively. 4. pre : all banks precharge is necessary. mrs can be issued only at all banks precharge state. 1 2 1 2 *4 trp 2clk trdl *1 tbdl *2 8. burst stop & interrupted by precharge 9. mrs 1) normal write d 0 d 1 d 2 2) write burst stop (bl=8) cmd dq clk dqm bl=4 & trdl=2clk wr pre clk cmd dqm dq wr stop d 0 d 1 d 2 d 3 3) read interrupted by precharge (bl=4) clk cmd dq(cl2) dq(cl3) rd pre q 0 q 1 q 0 q 1 4) read burst stop (bl=4) clk cmd dq(cl2) dq(cl3) rd stop q 0 q 1 q 0 q 1 1) mode register set clk cmd pre mrs act KBE00F005A-D411 mcp memory june 2005 64 revision 1.0 tss *1 tss *2 auto refresh command pre t rp(min) t arfc(min) auto cke = high refresh cmd an auto refresh command is issued by having cs , ras and cas held low with cke and we high at the rising edge of the clock(clk). all banks must be precharged and idle for t rp (min) before the auto refresh command is applied. no control of the external address pins is required once this cycle has started because of the internal address counter. when the refresh cycle has compl eted, all banks will be in the idle state. a delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the t arfc (min). clk a self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. once the self refresh command is initiated, cke must be held low to keep the device in self refresh mode. after 1 clock cycle from t he self refresh command, all of the external control signals including syst em clock(clk) can be disabled except cke. the clock is inte rnally disabled during self refresh operation to reduce power. to exit the self refresh mode, supply stable clock input before returni ng cke high, assert deselect or nop command and then assert cke high . in case that the system uses burst auto refresh during normal opreation, it is recommended to use burst 4096 auto refresh cycle immediately before entering self refresh mode and after exiti ng in self refresh mode. on the other hand, if the system uses t he distributed auto refresh, the syst em only has to keep the refresh duty cycle. self refresh command cke stable clock t ss nop self refresh clk t srfx(min) t ss act 10. clock suspend exit & power down exit 11. auto refresh & self refresh 1) clock suspend (=active power down) exit 2) power down (=precharge power down) exit clk cke internal clk cmd rd clk cke internal clk cmd nop act KBE00F005A-D411 mcp memory june 2005 65 revision 1.0 12. about burst type control basic mode sequential counting at mrs a 3 = "0". see the burst sequence table. (bl=4, 8) bl=1, 2, 4, 8 and full page. interleave counting at mrs a 3 = "1". see the burst sequence table. (bl=4, 8) bl=4, 8. at bl=1, 2 interleave counting = sequential counting. random mode random column access t ccd = 1 clk every cycle read/write command with random column address can realize random column access. that is similar to extended data out (edo) operation of conventional dram. 13. about burst length control basic mode 1 at mrs a 2,1,0 = "000". at auto precharge, t ras should not be violated. 2 at mrs a 2,1,0 = "001". at auto precharge, t ras should not be violated. 4 at mrs a 2,1,0 = "010". 8 at mrs a 2,1,0 = "011". full page at mrs a 2,1,0 = "111". wrap around mode(infinite burst length) should be stopped by burst stop. ras interrupt or cas interrupt. special mode brsw at mrs a 9 = "1". read burst =1, 2, 4, 8, full page write burst =1. at auto precharge of write, t ras should not be violated. random mode burst stop t bdl = 1, valid dq after burst stop is 1, 2 for cas latency 2, 3 respectively using burst stop command, any bur st length control is possible. interrupt mode ras interrupt (interrupted by precharge) before the end of burst, row precharge command of the same bank stops read/write burst with row precharge. t rdl = 2 with dqm, valid dq after burst stop is 1, 2 for cas latency 2, 3 respectively. during read/write burst with auto precharge, ras interrupt can not be issued. cas interrupt before the end of burst, new read/write stops read/write burst and starts new read/write burst. during read/write burst with auto precharge, cas interrupt can not be issued. KBE00F005A-D411 mcp memory june 2005 66 revision 1.0 function truth table (table 1) current state cs ras cas we ba address action note idle h x x x x x nop l h h h x x nop l h h l x x illegal 2 l h l x ba ca, a 10 /ap illegal 2 l l h h ba ra row (& bank) active ; latch ra l l h l ba a 10 /ap nop 4 l l l h x x auto refresh or self refresh 5 l l l l op code op code mode register access 5 row active h x x x x x nop l h h h x x nop l h h l x x illegal 2 l h l h ba ca, a 10 /ap begin read ; latch ca ; determine ap l h l l ba ca, a 10 /ap begin read ; latch ca ; determine ap l l h h ba ra illegal 2 l l h l ba a 10 /ap precharge l l l x x x illegal read h x x x x x nop (continue burst to end --> row active) l h h h x x nop (continue burst to end --> row active) l h h l x x term burst --> row active l h l h ba ca, a 10 /ap term burst, new read, determine ap l h l l ba ca, a 10 /ap term burst, new write, determine ap 3 l l h h ba ra illegal 2 l l h l ba a 10 /ap term burst, precharge timing for reads l l l x x x illegal write h x x x x x nop (continue burst to end --> row active) l h h h x x nop (continue burst to end --> row active) l h h l x x term burst --> row active l h l h ba ca, a 10 /ap term burst, new read, determine ap 3 l h l l ba ca, a 10 /ap term burst, new write, determine ap 3 l l h h ba ra illegal 2 l l h l ba a 10 /ap term burst, precharge timing for writes 3 l l l x x x illegal read with auto precharge h x x x x x nop (continue burst to end --> precharge) l h h h x x nop (continue burst to end --> precharge) l h h l x x illegal l h l x ba ca, a 10 /ap illegal l l h x ba ra, ra 10 illegal 2 l l l x x x illegal write with auto precharge h x x x x x nop (continue burst to end --> precharge) l h h h x x nop (continue burst to end --> precharge) l h h l x x illegal l h l x ba ca, a 10 /ap illegal l l h x ba ra, ra 10 illegal 2 l l l x x x illegal KBE00F005A-D411 mcp memory june 2005 67 revision 1.0 *note: 1. all entries assume the cke was active (high) du ring the precharge clock and the current clock cycle. 2. illegal to bank in specified state ; function may be iegal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba (and a 10 /ap). 5. illegal if any bank is not idle. abbreviations : ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge function truth table (table 1) current cs ras cas we ba address action note precharging h x x x x x nop --> idle after t rp l h h h x x nop --> idle after t rp l h h l x x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a 10 /ap nop --> idle after t rp 4 row activating l l l x x x illegal h x x x x x nop --> row active after t rcd l h h h x x nop --> row active after t rcd l h h l x x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a 10 /ap illegal 2 l l l x x x illegal refreshing h x x x x x nop --> idle after t rc l h h x x x nop --> idle after t rc l h l x x x illegal l l h x x x illegal l l l x x x illegal mode register accessing h x x x x x nop --> idle after 2 clocks l h h h x x nop --> idle after 2 clocks l h h l x x illegal l h l x x x illegal l l x x x x illegal KBE00F005A-D411 mcp memory june 2005 68 revision 1.0 function truth table (table 2) current state cke (n-1) cke n cs ras cas we address action note self refresh h x x x x x x exit self refresh --> idle after ts rfx (abi) l h h x x x x exit self refresh --> idle after ts rfx (abi) 6 l h l h h h x exit self refresh --> idle after ts rfx (abi) 6 l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self refresh) all banks precharge power down h x x x x x x invalid l h h x x x x exit power down --> abi l h l h h h x exit power down --> abi 7 l h l h h l x illegal 7 l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain low power mode) all banks idle h h x x x x x refer to table 1 h l h x x x x enter power down h l l h h h x enter power down 8 h l l h h l x illegal 8 h l l h l x x illegal h l l l h h ra row (& bank) active h l l l l h x enter self refresh 8 h l l l l l op code mode register access l l x x x x x nop any state other than listed above h h x x x x x refer to operations in table 1 h l x x x x x begin clock suspend next cycle 9 l h x x x x x exit clock suspend next cycle 9 l l x x x x x maintain clock suspend *note: 6. cke low to high transition is asynchronous. 7. cke low to high transition is asyn chronous if restarts internal clock. a minimum setup time 1clk + t ss must be satisfied before any command other than exit. 8. power down and self refresh can be entered only from the all banks idle state. 9. must be a legal command. abbreviations : abi = all banks idle, ra = row address KBE00F005A-D411 mcp memory june 2005 69 revision 1.0 power up sequence single bit read - write - read cycle(same page) @cas latency=3, burst length=1 read & write cycle at same b ank @burst length=4, trdl=2clk page read & write cycle at same bank @burst length=4, trdl=2clk page read cycle at different bank @burst length=4 page write cycle at different b ank @burst length=4, trdl=2clk read & write cycle at diff erent bank @burst length=4 read & write cycle with auto precharge l @burst length=4 read & write cycle with auto precharge ll @burst length=4 clock suspension & dqm operation cycle @cas letency=2, burst length=4 read interrupted by precharge command & read burst stop cycle @ full page burst write interrupted by precharge command & write burst stop cycle @ full page burst, trdl=2clk burst read single bit write cycle @burst length =2 active/precharge power dower down mode @cas latency=2 burst length=4 self refresh entry & exit cycle & exit cycle mode register set cycle and auto refresh cycle extended mode register set cycle KBE00F005A-D411 mcp memory june 2005 70 revision 1.0 0123456789101112131415 high level is necessary cke cs ras cas addr ba0 ba1 dq a10/ap we power up sequence for mobile sdram dqm precharge t rp 16 17 18 19 20 21 22 24 23 25 key raa hi-z hi-z t arfc t arfc (all bank) auto refresh auto refresh normal mrs extended mrs row active (a-bank) *note: 1. apply power and attempt to maintain cke at a high state and all other inputs may be undefined. - apply v dd before or at the same time as v ddq . 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. 6. issue a extended mode register set command to define ds or pasr operating type of the device after normal mrs. emrs cycle is not mandatory and the emrs command needs to be issued only when ds or pasr is used. the default state without emrs command issued is the half driver strength and full array refreshed. the device is now ready for the operation selected by emrs. for operating with ds or pasr , set ds or pasr mode in emrs setting stage. in order to adjust another mode in the state of ds or pasr mode, additional emrs set is required but power up sequence is not needed again at this time. in that case, all banks have to be in idle state prior to adjusting emrs set. : don?t care key clock hi raa KBE00F005A-D411 mcp memory june 2005 71 revision 1.0 012345678910111213141516171819 cke cs ras cas ba0,ba1 a10/ap we addr dqm : don?t care clock single bit read-write-read cycle(same page) @cas latency=3, burst length=1 high ra ca bs bs ra dq row active read write read row active precharge t cc t ch t cl t ras t rc t sh t ss *note 1 t rcd t rp t sh t ss t sh t ss t sh t ss *note 2 *note 2,3 *note 2,3 *note 2,3 *note 4 *note 2 *note 3 *note 3 *note 3 *note 4 t ss t sh t oh t slz t sac t sh t ss t sh t ss *note: 1. all input except cke & dqm can be don't care when cs is high at the clk high going edge. 2. bank active & read/write are controlled by ba0,ba1. cb cc rb bs bs bs bs qa db qc rb KBE00F005A-D411 mcp memory june 2005 72 revision 1.0 012345678910111213141516171819 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock read & write cycle at same ba nk @burst length=4, trdl=2clk high ra ca ra cl=2 row active read write precharge t rc *note 1 t shz t sac t oh *note: 1. minimum row cycle times is required to complete internal dram operation. 2. row precharge can interrupt burst on any cycle. [cas latency - 1] number of valid output data is available after row precharge. last valid output will be hi-z(t shz ) after the clcok. 3. ouput will be hi-z after the end of burst. (1, 2, 4, 8 & full page bit burst) ba0 dqm dq t rdl *note 2 *note 4 t shz t sac t oh t rdl *note 4 (a-bank) (a-bank) (a-bank) (a-bank) row active (a-bank) precharge (a-bank) { t rcd qa1 db0 qa0 qa2 db1 db2 db3 qa3 qa1 db0 qa0 qa2 db1 db2 db3 qa3 rb rb cb KBE00F005A-D411 mcp memory june 2005 73 revision 1.0 012345678910111213141516171819 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock page read & write cycle at same bank @burst length=4, trdl=2clk high ra ca ra cl=2 row active read write precharge *note: 1. to write data before burst read ends, dqm should be asserted three cycle prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input, t rdl before row precharge, will be written. 3. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 4. t dal ,last data in to active delay, is 2clk + t rp . ba0 dqm dq t rdl *note 3 (a-bank) (a-bank) (a-bank) (a-bank) { *note 2 cb t dal *note 4 *note 1 t cdl read (a-bank) write (a-bank) row active (a-bank) cc cd rb rb qa1 dd0 qa0 qb0 dd1 qb1 qb2 dc0 dc1 qa1 dd0 qa0 qb0 dd1 qb1 dc0 dc1 t rcd KBE00F005A-D411 mcp memory june 2005 74 revision 1.0 012345678910111213141516171819 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock page read cycle at different bank @burst length=4 high raa caa raa cl=2 row active read precharge *note: 1. cs can be don't cared when ras , cas and we are high at the clock high going dege. 2. to interrupt a burst read by row precharge, both the read and the precharge banks must be the same. ba0 dqm dq (a-bank) (a-bank) (d-bank) { *note 2 rcc read (b-bank) cbb rdd ccc cdd rbb rcc rdd qaa1 qaa2 qbb0 qbb1 qbb2 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 qaa1 qaa2 qbb0 qbb1 qbb2 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 row active (b-bank) row active (c-bank) row active (d-bank) precharge (a-bank) read (c-bank) precharge (b-bank) read (d-bank) precharge (c-bank) *note 1 qaa0 qaa0 rbb KBE00F005A-D411 mcp memory june 2005 75 revision 1.0 012345678910111213141516171819 cke cs ras cas ba1 a10/ap addr we : don?t care clock page write cycle at different ba nk @burst length=4, trdl=2clk high raa row active write write precharge *note: 1. to interrupt burst write by row precharge, dqm should be asserted to mask invalid input data. 2. to interrupt burst write by row precharge, both the write and the precharge banks must be the same. ba0 dqm dq *note 1 (a-bank) (a-bank) (d-bank) (all banks) *note 2 rab caa cbb rcc rdd ccc raa rbb rcc rdd daa3 dbb0 dbb1 dbb2 dbb3 dcc0 dcc1 ddd0 ddd1 ddd2 t cdl t rdl row active (b-bank) write (b-bank) row active (c-bank) row active (d-bank) write (c-bank) daa2 daa1 daa0 cdd KBE00F005A-D411 mcp memory june 2005 76 revision 1.0 012345678910111213141516171819 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock read & write cycle at different bank @burst length=4 high raa raa cl=2 row active read write read *note: 1. t cdl should be met to complete write. ba0 dqm dq (a-bank) (a-bank) (d-bank) (b-bank) precharge (a-bank) { caa rdb rbc cbc rdb t cdl *note 1 row active (d-bank) row active (b-bank) qaa1 qaa0 qaa2 qaa3 qbc0 qbc1 qbc2 ddb0 ddb1 ddb2 ddb3 qaa1 qaa0 qaa2 qaa3 qbc0 qbc1 cdb rbc ddb0 ddb1 ddb2 ddb3 KBE00F005A-D411 mcp memory june 2005 77 revision 1.0 012345678910111213141516171819 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock read & write cycle with auto precharge i @burst length=4 high raa raa cl=2 row active read with precharge row active *note: 1. when read(write) command with auto precharge is issued at a-bank after a and b bank activation. - if read(write) command without auto precharge is issued at b-bank before a-bank auto precharge starts, a-bank auto precharge will start at b-bank read command input point . - any command can not be issued at a-bank during t rp after a-bank auto precharge starts. ba0 dqm dq (a-bank) auto pre (b-bank) (a-bank) read without auto precharge(b-bank) rbb rac cac caa cbb rbb dac0 dac0 charge (a-bank) row active (b-bank) auto precharge start point (a-bank) *note1 write with auto precharge (a-bank) qaa1 qaa0 qbb0 qbb1 dbb3 qbb2 qaa1 qaa0 qbb0 qbb1 dbb3 qbb2 dac1 dac1 rac KBE00F005A-D411 mcp memory june 2005 78 revision 1.0 012345678910111213141516171819 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock read & write cycle with auto precharge ii @burst length=4 high ra cl=2 row active read with *note: 1. any command to a-bank is not allowed in this period. t rp is determined from at auto precharge start point ba0 dqm dq (a-bank) auto precharge auto precharge start point ca rb (a-bank) (a-bank) row active (b-bank) *note1 cb read with auto precharge (b-bank) auto precharge start point (b-bank) rb qa1 qa0 qa2 qa3 qb1 qb0 qb2 qb3 qa1 qa0 qa2 qa3 qb1 qb0 qb2 qb3 ra KBE00F005A-D411 mcp memory june 2005 79 revision 1.0 012345678910111213141516171819 cke cs ras cas ba1 a10/ap addr we : don?t care clock clock suspension & dqm operation cycle @cas latency=2, burst length=4 ra row active read write *note: 1. dqm is needed to prevent bus contention. ba0 dqm dq *note 1 dqm ca qb0 qb1 dc0 dc2 clock suspension write cb ra t shz t shz read clock suspension write dqm read dqm qa1 qa2 qa3 qa0 cc KBE00F005A-D411 mcp memory june 2005 80 revision 1.0 012345678910111213141516171819 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock read interrupted by precharge command & read burst stop cycle @full page burst high raa cl=2 row active *note: 1. at full page mode, burst is finished by burst stop or precharge. 2. about the valid dqs after burst stop, it is same as the case of ras interrupt. both cases are illustrated above timing diagram. see the label 1, 2 on them. but at burst write, burst stop and ras interrupt should be compared carefully. refer the timing diagram of "full page write burst stop cycle". 3. burst stop is valid at every burst length. ba0 dqm qaa3 (a-bank) caa cab burst stop precharge (a-bank) dq { qaa4 1 1 qaa2 qaa3 qaa4 2 raa read (a-bank) read (a-bank) qaa1 qaa0 qaa2 qaa1 qaa0 qab1 qab0 qab2 qab3 qab4 qab5 qab1 qab0 qab2 qab3 qab4 qab5 2 KBE00F005A-D411 mcp memory june 2005 81 revision 1.0 012345678910111213141516171819 cke cs ras cas ba1 a10/ap addr we : don?t care clock write interrupted by precharge command & write burst stop cycle @ full page burst, raa row active write *note: 1. at full page mode, burst is finished by burst stop or precharge. 2. data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. it is defined by ac parameter of t rdl . dqm at write interrupted by precharge command is needed to prevent invalid write. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 3. burst stop is valid at every burst length. ba0 dqm dq caa cab burst stop high raa daa3 daa4 dab0 dab1 dab2 dab3 dab4 dab5 t bdl *note 1 t rdl *note 1,2 (a-bank) (a-bank) write (a-bank) precharge (a-bank) trdl=2clk daa2 daa1 daa0 KBE00F005A-D411 mcp memory june 2005 82 revision 1.0 012345678910111213141516171819 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock burst read single bit write cycle @burst length=2 high raa cl=2 row active *note: 1. brsw modes is enabled by setting a9 "high" at mrs (mode register set). at the brsw mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. when brsw write command with auto precharge is executed, keep it in mind that t ras should not be violated. auto precharge is executed at the burst-end cycle, so in the case of brsw write command, the next cycle starts the precharge. ba0 dqm (a-bank) caa rcc precharge (c-bank) dq { raa write (a-bank) *note 2 rbb cab cbc ccd rbb rcc row active (b-bank) read with auto precharge (a-bank) row active (c-bank) write with auto precharge (b-bank) read (c-bank) daa0 qab0 qab1 dbc0 qcd0 qcd1 daa0 qab0 qab1 dbc0 qcd0 qcd1 KBE00F005A-D411 mcp memory june 2005 83 revision 1.0 012345678910111213141516171819 cke cs ras cas a10/ap addr we : don?t care clock active/precharge power down mode @cas latency=2, burst length=4 precharge row active precharge *note: 1. all banks should be in idle state prior to entering precharge power down mode. 2. cke should be set high at least 1clk + t ss prior to row active command. 3. can not violate minimum refresh specification. (64ms) ba dqm dq *note 1 power-down *note 2 ra ca qa0 qa1 qa2 precharge power-down read ra t shz *note 2 entry exit active power-down entry active power-down exit t ss *note 3 t ss t ss KBE00F005A-D411 mcp memory june 2005 84 revision 1.0 012345678910111213141516171819 cke cs ras cas a10/ap addr we : don?t care clock self refresh entry & exit cycle self refresh entry *note: to enter self refresh mode 1. cs , ras & cas with cke should be low at the same clcok cycle. 2. after 1 clock cycle, all the inputs including the system clock can be don't care except for cke. 3. the device remains in self refresh mode as long as cke stays "low". cf.) once the device enters self refresh mode, minimum t ras is required before exit from self refresh. to exit self refresh mode 4. system clock restart and be stable before returning cke high. 5. cs starts from high. 6. minimum t srfx is required after cke going high to complete self refresh exit. 7. 4k cycle(64mb ,128mb) or 8k cycle(256mb, 512mb) of bu rst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. ba0,ba1 dqm dq *note 1 *note 4 t ss *note 3 t srfx *note 2 *note 6 self refresh exit auto refresh hi-z hi-z KBE00F005A-D411 mcp memory june 2005 85 revision 1.0 0123456 0 10 cke cs ras cas ba1 addr we : don?t care clock mode register set cycle key mrs new command *note: mode register set cycle 1. cs , ras , cas , ba0, ba1 & we activation at the same clock cycle with address key will set internal mode register. 2. minimum 2 clock cycles should be met before new ras activation. 3. please refer to mode register set table. ba0 dqm dq ra auto refresh auto refresh cycle 123456789 high high new command * all banks precharge should be completed before mode register set cycle and auto refresh cycle. *note 2 *note 1 *note 3 t arfc hi-z hi-z KBE00F005A-D411 mcp memory june 2005 86 revision 1.0 0123456 cke cs ras cas ba1 addr we : don?t care clock extended mode register set cycle key emrs new command *note: extended mode register set cycle 1. cs , ras , cas , ba0, ba1 & we activation at the same clock cycle with address key will set internal mode register. 2. minimum 2 clock cycles should be met before new ras activation. 3. please refer to mode register set table. ba0 dqm dq ra high *note 2 *note 1 *note 3 hi-z KBE00F005A-D411 mcp memory june 2005 87 revision 1.0 package dimension units:millimeters 0.10 max 0.45 0.05 0.32 0.05 1.30 0.10 top view 10.50 0.10 13.00 0.10 #a1 13.00 0.10 137- ? 0.45 0.05 0 . 8 0 0.20 m a b ? (datum a) 1 42 765 3 8 #a1 index mark 10.50 0.10 1 3 . 0 0 0.10 0 . 8 0 9 10 0.80x9=7.20 0 . 8 0 x 1 4 = 1 1 . 2 0 a b c e g d f h j l k m n r (datum b) 5 . 6 0 3.60 a b bottom view p 137-ball fine pitch ball grid array package (measured in millimeters) |
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